In the production of integrated circuit chips, it is important that all of the various circuits on the integrated circuit chips are tested prior to incorporating the various chips into completed systems. As the complexity of integrated circuit chips increases, the difficulty of performing one hundred percent testing of all of the circuit components becomes challenging. One area where such 100% testing has been difficult is in the testing of asynchronous ripple counters. Generally, such ripple counters are not scannable, because only one flip-flop in the counter chain is connected to the master clock. Synchronous counters, in contrast, are easily scannable; but these counters consume significant amounts of power, since all of the flip-flops are connected to the master clock.
In order to test asynchronous counters, the counters generally are split into a plurality of four-bit counters tested in partial scan methodology. Since skew problems arise in deep sub-micron technology, the designers of such counters are forced to insert lockup latches between the scan elements. This leads to a large amount of added gates and even greater power consumption, since the lockup latches consume power in their functional mode.
It is desirable to design a low power scannable asynchronous counter which overcomes the disadvantages of the prior art, which is easy to scan, which is one hundred percent testable, and which consumes low power in its functional operating mode.